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Paper · 2003.06308 · 2020

Compressing deep neural networks on FPGAs to binary and ternary precision with HLS4ML

arXiv · PDF · Open in the Atlas

Code that ran

We lifted 6 functions out of this paper's own repositories and ran 3 of them in a sandbox. "Ran" means the function executed on a synthesized input and returned a value. It is not a reproduction of the paper's results.

RepositoryRoleRan
hls-fpga-machine-learning/hls4ml canonical 3 of 6
FunctionStatusWhere it lives
array_to_summary Ran hls-fpga-machine-learning/hls4ml/hls4ml/model/profiling.py
code served (permissive licence) · get_code("254e7a84dc620a57")
boxplot Ran hls-fpga-machine-learning/hls4ml/hls4ml/model/profiling.py
code served (permissive licence) · get_code("f5cba7fafe8166fd")
find_minimum_width Ran hls-fpga-machine-learning/hls4ml/hls4ml/model/types.py
code served (permissive licence) · get_code("bee79d98e7582bd9")
fetch_example_model Not yet run hls-fpga-machine-learning/hls4ml/hls4ml/utils/example_models.py
code served (permissive licence) · get_code("8ff9eaa80ce13603")
get_backend Not yet run hls-fpga-machine-learning/hls4ml/hls4ml/backends/backend.py
code served (permissive licence) · get_code("1242fc9c36f9fde0")
get_unoptimized_hlsmodel Not yet run hls-fpga-machine-learning/hls4ml/hls4ml/model/profiling.py
code served (permissive licence) · get_code("a0f249e116bdec49")

Repositories linked to this paper

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Abstract

We present the implementation of binary and ternary neural networks in the hls4ml library, designed to automatically convert deep neural network models to digital circuits with FPGA firmware. Starting from benchmark models trained with floating point precision, we investigate different strategies to reduce the network's resource consumption by reducing the numerical precision of the network parameters to binary or ternary. We discuss the trade-off between model accuracy and resource consumption. In addition, we show how to balance between latency and accuracy by retaining full precision on a selected subset of network components. As an example, we consider two multiclass classification tasks: handwritten digit recognition with the MNIST data set and jet identification with simulated proton-proton collisions at the CERN Large Hadron Collider. The binary and ternary implementation has similar performance to the higher precision implementation while using drastically fewer FPGA resources.

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